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Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles
book

Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

by James S. Evans - Lawrence University, Gregory L. Trimper - viika
April 2003
Intermediate to advanced content levelIntermediate to advanced
576 pages
15h 13m
English
Pearson
Content preview from Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

7.3. Register Stacks

Stacks can be implemented in memory or as a bank of registers. Although a stack composed of processor registers can offer significant performance increases, greater cost and small register counts precluded realistic consideration until RISC designs emerged. The reduction in circuitry required to recognize and execute complex instructions released space on a processor chip for other uses, including more on-chip cache and a larger pool of registers.

7.3.1. SPARC® Register Windows

Research in computer architecture at the University of California–Berkeley led to the creation of the SPARC® architecture by Sun® Microsystems.

Early implementations of the SPARC architecture devoted a significant portion of the processor chip to registers. ...

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Publisher Resources

ISBN: 0131013726Purchase book