September 2003
Intermediate to advanced
1120 pages
23h 44m
English
Figure 22-13 on page 803 illustrates the layout of a PCI-to-PCI bridge's configuration header space.
The Header Type 1 PCI configuration registers that are implemented and used identically in both PCI and PCI Express are:
Vendor ID register.
Device ID register.
Revision ID register.
Class Code register.
Header Type register.
BIST register.
Capabilities Pointer register.
Subordinate Bus Number register.
Secondary Bus Number register.
Primary Bus Number register.
IO Base, Limit and Upper registers.
Memory Base and Limit registers.
Expansion ROM Base Address register.
The sections that follow provide a description of each of these registers.
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