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39DC-DC Converter Design and Magnetics

Note also, that for any topology, a high duty cycle corresponds to a low input voltage,

and a lo

w duty cycle is equivalent to a high input. So increasing D amounts to decreasing

the input voltage (its magnitude) in all cases. Therefore, in a boost or buck-boost, if the

difference between the input and output voltages is large, we get the highest DC inductor

current.

Finally, with the DC and AC components known, we can calculate the peak current using

III

I

I

PK AC DC L

2

(3-9)

3.5 Deﬁ ning the “ Worst-case ” Input Voltage

So far, we have been implicitly assuming a ﬁ xed input voltage. In reality, in most practical

applications, the input voltage is a certain range , say from V

INMIN

to V

INMAX

.

We therefore also need to know how the AC, DC, and peak current components change

as we vary the input voltage . Most importantly, we need to know at what speciﬁ c voltage

within this range we get the maximum peak current. As mentioned, the peak is critical

from the standpoint of ensuring there is no inductor saturation . Therefore, deﬁ ning the

“ worst-case ” voltage (for inductor design) as the point of the input voltage range where

the peak current is at its maximum, we need to design/select our inductor at this particular

point always. This is in fact the underlying basis of the general inductor design procedure

that we will be presenting soon.

We will now try to understand where and why we get the highest peak currents for

each topology. In Figure 3.3 , we have drawn various inductor current waveforms to

help us better visualize what really happens as the input is varied. We have chosen two

topologies here, the buck and the buck-boost, for which we display two waveforms each,

corresponding to two different input voltages. Finally, in Figure 3.4 we have plotted

out the AC, DC, and peak values. Note that these plots are based on the actual design

equations, which are also presented within the same ﬁ gure. While interpreting the plots,

we should again keep in mind that for all topologies, a high D corresponds to a low input.

The following analysis will also explain certain cells of the previously provided Table 3.2 ,

where the variations of I and I

DC

, with respect to D , were summarized.

a ) For the buck , the situation can be analyzed as follows:

• As the input increases , the duty cycle decreases in an effort to maintain

regulation. But the slope of the down-ramp I/t

OFF

cannot change , because

it is equal to V

OFF

/ L , that is, V

O

/ L , and we are assuming V

O

is ﬁ xed. But now,

since t

OFF

has increased, but the slope I / t

OFF

has not changed, the only

possibility is that I must have increased (proportionally). So we conclude

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