September 2008
Beginner
834 pages
37h 13m
English
Fig. 2.3-1 Two Ideal Independent Voltage Sources in Parallel
Interconnecting two or more ideal voltage sources in a loop may lead to a degenerate circuit at times. Similarly, interconnecting two or more ideal current sources in series may lead to a degenerate circuit.
Consider the interconnection of two ideal independent voltage sources as shown in Fig. 2.3-1. KVL requires that –vs1(t) + vs2(t) = 0. Therefore, vs1(t) has to be equal to vs2(t) at all time instants. If they are not equal to each other, then, either KVL has to yield or the ideal sources have to yield. KVL cannot yield since it is only ...
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