Hands-On High Performance Programming with Qt 5

Atomic operation costs

At least on the Intel architecture, atomic operations, also called Cache Acceleration Software (CAS), are implemented by using the LOCK instruction prefix. In older Intel architectures, this would block the bus and thus all memory operations on all cores, incurring rather a high overhead on atomics. However, newer Intel processors will only block the relevant cache line, significantly reducing the costs.

Additionally, if we require a sequential memory ordering, a memory fence will be needed, flushing all the pending writes and stalling the pipeline. We can work around this in C++ using relaxed memory orderings, but we won't discuss this advanced topic further in this book.

As may be seen, atomic operation on modern ...