8.1. Introduction

The design of wireless protocols and their implementations on heterogeneous architectures, including dedicated IP, programmable logic, and one or more embedded processors, is a difficult task. One challenge is to provide validation and performance estimation of a given mapping of the protocol functionalities on the architecture without doing cycle-accurate simulation at the register-transfer level (RTL). This allows a pragmatic approach to architecture and application performance optimization, in an attempt to achieve both flexibility and efficiency, by running simulations with several test benches. Despite the high level of abstraction used in the modeling of both the application and the architecture components (programmable ...

Get Multiprocessor Systems-on-Chips now with O’Reilly online learning.

O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.