October 2004
Intermediate to advanced
608 pages
17h 1m
English
Content preview from Multiprocessor Systems-on-Chips
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8.6. Results
This section presents the results of some explorations that we performed, by evaluating the different mapping scenarios listed in Figure 8-13 for the transmitter application shown in Figure 8-7, using the architectural model of the datapath shown in Figure 8-8.
We report the global latency and throughput effects of the architectural choices, such as memory configuration (single port versus multiple ports),
Figure 8-13. Explored design space for transmitter application.
communication refinement (direct connect versus shared memory), and ...
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