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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

Name: Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems
ISBN: 9780471556657

by John V. Oldfield, Richard C. Dorf

January 1995

Intermediate to advanced

360 pages

English

Wiley-Interscience

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Coverpage
Titlepage
Copyright
Dedication
Contents
Foreword
Preface
Acronyms
Trademarks and Proprietary Names
1. SYSTEM IMPLEMENTATION STRATEGIES

1.1 The FPGA Paradigm
1.2 Design and Implementation Using FPGAs
1.3 Implementation Styles
1.3.1 Era of Early Logic Families1.3.2 Era of LSI and VLSI Components1.3.3 Era of ASICs1.3.4 Era of Programmable Logic
1.4 Design Styles
1.4.1 The Software Paradigm1.4.2 The Hardware Paradigm1.4.3 The Configurable Hardware Paradigm
1.5 Design Methodologies
1.5.1 Describing a Design1.5.2 Hierarchical Design1.5.3 Technology-independent Design1.5.4 The Mead–Conway Design Method1.5.5 Temporal Design1.5.6 Pipelined1.5.7 Unsynchronized
2. REVIEW OF LOGIC DESIGN AND ELECTRICAL ASPECTS
2.1 Combinational Circuit Design
2.1.1 Boolean Algebra2.1.2 Multiplexers and Boolean Function Evaluation
2.2 Sequential Circuits
2.2.1 Latches and Flip-Flops
2.3 State Machines
2.3.1 Encoded State Machines2.3.2 “One-hot” State Machines
2.4 Petri Nets for State Machines
2.4.1 Basic Concepts2.4.2 Basic Properties2.4.3 Extended Petri Nets for Parallel Controllers2.4.4 Simple Example—A Traffic Light Controller2.4.5 Implementation of Petri Net Description
2.5 Electrical Aspects
2.5.1 Complementary MOS Circuits2.5.2 Voltage Levels and Loading2.5.3 Three-state Outputs2.5.4 Signal Propagation in CMOS2.5.5 Electrostatic Precautions and ESD Protection2.5.6 Switch Debouncing2.5.7 Power Supply Regulation2.5.8 Metastability Characteristics
3. INTRODUCTION TO FPGA ARCHITECTURE
3.1 Background to the FPGA Concept
3.1.1 History
3.2 Channel-type Field-programmable Gate Arrays
3.2.1 Distinguishing Architectural Features3.2.2 Scaling with Technology Improvements3.2.3 The Xilinx 3000 Series3.2.4 The Actel ACT 2 Family
3.3 Structured Programmable Array Logic
3.3.1 The Altera EP1810
3.4 Computational Logic Arrays
3.4.1 The Algotronix CAL 1024
3.5 VLSI Primitives
3.5.1 Function Units3.5.2 Wide Gates and Long Lines3.5.3 Switches and Switch Boxes3.5.4 Multiplexers3.5.5 Input–Output Pad Design
3.6 Programming
3.6.1 Technology3.6.2 Issues
3.7 Benchmarking
3.7.1 Utilization3.7.2 Gate Equivalents3.7.3 RAM- and Area-based Benchmarks3.7.4 Benchmarking and Dynamic Reconfiguration3.7.5 The PREP Benchmarks3.7.6 Summary and Health Warning
3.8 Historical Background
3.8.1 Early Work3.8.2 PALs and Structured PALs3.8.3 FPGAs3.8.4 Computational Arrays3.8.5 VLSI Primitives and Programming3.8.6 Benchmarking
4. DESIGN PROCESS FLOWS AND SOFTWARE TOOLS
4.1 The Software Toolbox
4.1.1 Design Capture4.1.2 Tools for Design Validation4.1.3 Tools for Physical Design
4.2 The FPGA Design Dichotomy
4.3 Design Process Flow
4.3.1 Conceptual Design of Display Driver4.3.2 Design Verification of Display Driver4.3.3 Physical Design of Display Driver
4.4 Design Process Flow: The Application-specific Integrated Circuit Route
4.4.1 Conceptual Design of Stopwatch4.4.2 Design Verification of Stopwatch4.4.3 Physical Design of Stopwatch
4.5 Libraries and Design Idioms
4.5.1 Parameterized Libraries
4.6 Placement, Routing, and Wireability
4.6.1 Rent’s Rule and Package Pin-outs4.6.2 Rent’s Rule and Wireability4.6.3 Partitioning Designs within and across Chips
5. CASE STUDIES
5.1 Combinational Circuits
5.1.1 Parallel Adder Cell5.1.2 Parallel Adder
5.2 Sequential Circuits
5.2.1 Decade Counter
5.3 Pseudorandom Number Generation
5.4 Random Testing
5.4.1 Signature Analyzer5.4.2 State Machine
5.5 Systolic Sorter
5.6 Multipliers
5.6.1 Parallel Multipliers5.6.2 Serial Multiplier with Parallel Addition
5.7 A Parallel Controller Design
5.7.1 Operation of Part of the Petri Net Controller5.7.2 Characteristics of the Design Technique5.7.3 Implementation on XC30905.7.4 Conclusions
6. COMPUTATIONAL APPLICATIONS
6.1 The State of the Art
6.2 Architecture of the CHS2×4
6.2.1 Hardware Architecture
6.3 DES Encryption
6.3.1 The DES Process6.3.2 Implementation of DES6.3.3 Pipelining6.3.4 Performance
6.4 Self-timed First-In First-Out Buffer
6.4.1 STEP Elements6.4.2 CAL Implementation6.4.3 Filling the Self-timed FIFO6.4.4 Designing in CAL6.4.5 A Full-custom Self-timed FIFO6.4.6 Conclusions
6.5 Self-timed Genetic String Distance Evaluation
6.5.1 String Comparison6.5.2 Genetic Sequence Comparison6.5.3 Dynamic Programming Algorithm6.5.4 Implementation Considerations6.5.5 Performance Evaluation6.5.6 The Self-timed Implementation
6.6 Cellular Automaton
6.6.1 The Model6.6.2 Architecture6.6.3 Comparison with Previous Systems6.6.4 Conclusion
6.7 Place-and-Route Acceleration
6.7.1 The Global Routing Algorithm6.7.2 Hardware Architecture6.7.3 CAL Layout6.7.4 Software6.7.5 Performance
6.8 A Field-Programmable Gate Array for Systolic Computing
6.8.1 Introduction6.8.2 CLi6000 Architecture6.8.3 Motion Estimation6.8.4 Algorithm Overview6.8.5 Processing Elements6.8.6 Absolute-difference Module and Accumulator6.8.7 Processing-element Layout6.8.8 Technology Comparisons6.8.9 Conclusions
7. BUSINESS DEVELOPMENT
7.1 Technology Push or Market Pull?
7.2 The Pioneers
7.3 FPGA Market and Start-up Companies
7.3.1 Rapid Prototyping7.3.2 Logic Replacement7.3.3 Arrays of FPGA Chips7.3.4 Dynamic Reconfiguration7.3.5 Do You Need a Fabrication Facility?
7.4 The MPGA as an Alternative to the FPGA for Low-volume Production
7.5 Intellectual Property
7.5.1 Patents7.5.2 Copyrights7.5.3 The Semiconductor Chip Protection Act of 19847.5.4 Trade Secrets7.5.5 Reverse Engineering
7.6 Sources for Capital
7.6.1 Small Business Innovation Research7.6.2 Small Business Technology Transfer Program
8. RECENT DEVELOPMENTS
8.1 Introduction
8.2 New Architectures
8.2.1 Altera FLEX8.2.2 Pilkington (Motorola/Plessey/Toshiba)8.2.3 Xilinx XC4000 Family
8.3 Field-programmable Interconnect
8.3.1 Aptix Field-programmable Interconnect8.3.2 I-Cube IQ160 Description
8.4 Configurable Logic Arrays and Prototyping Boards
8.4.1 The XESS RIPP Board
8.5 CAD Support
8.5.1 NeoCAD Foundry
8.6 Future Outlook
AFTERWORD
GLOSSARY
INDEX

Content preview from Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

5.3 PSEUDORANDOM NUMBER GENERATION

Random numbers can be very useful in simulation and testing digital circuits. Here we will use these numbers in testing the parallel adder described earlier. The term pseudorandom is used because the process is in fact completely predictable. The linear feedback shift register (LFSR) method is a particularly simple one, which can generate a sequence of length 2ⁿ – 1 for a register n bits long, provided it has the correct feedback connections. Figure 5–20 shows a 4-bit LFSR that can generate a sequence of length 15, not including the all-Is state, which is a lock-up state—once entered, the register will stay in this state indefinitely. Table 5–2 shows the feedback connections to produce a maximal length sequence for various register lengths.

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