Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

4.2   THE FPGA DESIGN DICHOTOMY

One of the interesting properties of FPGAs is that they merge what up until now have been two diverging families of electronic products: programmable logic devices, notably PALs, and ASICs, notably gate arrays and cell-based ICs. Each strand imposed a different implementation style on the engineer, each came with its preferred design process flow, and each came with its preferred toolset. The following sections set out to show explicitly how FPGAs can be designed either from an ASIC or PLD perspective.

Parenthetically, it is too simple to suggest that only two design methodologies and toolsets are important. In reality methodologies should be designed and toolsets chosen to match the end FPGA application. For example, one could classify the chief applications areas of programmable logic as: ASIC, ASIC emulation, and algorithm implementation/coprocessing, in which case the following observations would be relevant to method and toolset.

ASIC

Simple ASIC: A PAL design methodology that places emphasis on tools for capturing a behavioral description, optimizing logic equations and fitting the design to a member of a standard part catalog.

Complex ASIC: ASIC design places emphasis on both high-functionality tools for tasks like synthesis and automatic place-and-route, and low-level tools for complete design control and low-level optimization. More details are contained in the following sections.

ASIC Prototyping: The assumption here is that the real implementation ...