5.1.1   Parallel Adder Cell

The simplest form of parallel adder is a ripple adder, which consists of a cascade of 1-bit full adder cells. Each cell has inputs A, B along with carry input C. It produces outputs SUM and CARRY, determined by the Boolean equations for a full adder, corresponding to the truth table shown in Table 5–1.

SUM = A.Image.Image. + Ā.B.Image + Ā.Image.C + A.B.C

CARRY = A.B + A.C + B.C

Xilinx Implementation  The equations may be entered directly as the F and G outputs of a Xilinx 3000 series Configurable Logic Block (CLB), since each output can be an arbitrary function of up to four variables chosen from a total of five inputs. Since the functions are implemented by look-up tables, there is no advantage in manipulating the equations further. For such a simple case it is easy to enter the details directly on the CLB array with the editor XACT. Figure 5–2 shows the block concerned, while Figure 5–3 shows the routing to input and output pads. The routing was determined by XACT after each net had been given as a list of pins. The configuration of each input or ...

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