Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

8.2   NEW ARCHITECTURES

The chapter opens with some new FPGA architectures for reprogrammable FPGAs. We have deliberately excluded fuse- and electrically programmable FPGAs. Readers may note the wide range of approaches at both ends of the spectrum from fine- to coarse-grain, and the importance of wire delays—dynamic reprogrammability does not come for free. It is interesting to note that “dynamic” includes the possibility of reconfiguration while FPGA logic is active. Until recently virtually all manufacturers chose a serial loading process which implied that any change required a total reconfiguration, even for a single bit. Clearly most present-day applications do not require truly dynamic reconfigurability, but new applications may well exploit it, and this will require total reconsideration of CAD support and the host environment in cases where the FPGA is interfaced to a host computer.

8.2.1   Altera FLEX

Altera has developed four generations of complex programmable logic devices (CPLDs). The various families of devices are Classic, MAX 5000, MAX 7000, and FLEX 8000. While there are many differences in architectural details of these three families, there are some significant similarities as well. The similarities are a rich (nonblocking, local/global) interconnection scheme, and a coarse-grain/fine-grain logic architecture (groups of logic elements in clusters called logic array blocks (LABs)). The following is a brief description of the FLEX 8000 family.

FLEX 8000   The ...