High-Performance Embedded Computing

74 Chapter 2 CPUs

The C55x microarchitecture includes three data read and two data write bus-

ses in addition to the program read bus.

The C55x pipeline, which is divided into two stages as shown here, is longer

than that of the C54x, and it has a more complex structure. The fetch stage takes

four clock cycles; the execute stage takes seven or eight cycles.

During fetch, the prefetch 1 stage sends an address to memory, while

prefetch 2 waits for the response. The fetch stage gets the instruction. Finally,

the predecode stage sets up decoding.

During execution, the decode stage decodes a single instruction or instruc-

tion pair. The address stage performs ...