High-Performance Embedded Computing

3.4 Program Performance Analysis 185

addressed. Provided that the bus protocol is properly designed, the memory sys-

tem can start one access in one bank by presenting an address to that bank, then

start a second access to a different bank while waiting for the first access to

complete.

Panda [Pan99c] designed a custom memory system with multiple memory

banks for arrays. Grun et a.l [Gru00] used a timing analyzer to help schedule

instructions. They modeled the pipeline and memory to determine the actual

delay of a memory access based on the pipeline state.

Just as we need to know the speed at which hardware modules execute to design

a hardware system, ...