High-Performance Embedded Computing

3.4 Program Performance Analysis 195

■ First miss—Guaranteed not to be in the cache on the first loop iteration but

may be on later iterations.

■ First hit—Instruction may be in the cache on the first loop iteration but is

guaranteed not to be in the cache for later iterations.

To analyze the behavior of the instructions in the pipeline, Healy et al. used a

table to describe, for each type of instruction, worst-case and best-case number

of cycles required at every stage of the pipeline. They analyzed the iterations in

a loop iteration or single invocation of a function, which could consist of multi-

ple basic blocks. Their algorithm for determining ...