High-Performance Embedded Computing

2.9 Automated CPU Design 147

largest template (in the dotted line) can be used only three times in the computa-

tion, but the smaller graph (in the solid line) can be used six times.

instructions in

combination

Sun et al. [Sun04] developed an instruction set synthesis system that used the

Tensilica Xtensa system to implement their choices. Their system generates TIE

code that can be used to synthesize processors. They generate instructions from

Figure 2-53 A nonconvex operator graph.

Figure 2-54 Instruction template size versus utilization. From Biswas et al. [Bis05] © 2005

IEEE Computer Society.

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