High-Performance Embedded Computing

124 Chapter 2 CPUs

Control signals from the CPU determine the timing of the memory operation.

Segmenting the memory access into two parts allows arbitrary locations to be

modified without interfering with the execution of the code that governs the

memory modification. Because of the registers and control logic, even the loca-

tions that control the memory operation can be overwritten without causing

operational problems.

The next two examples introduce security features on two embedded proces-

sor families.

Example 2-10

SmartMIPS

The SmartMIPS extensions to the MIPS32 architecture [MIP05] are designed

for smart card systems. It provides instruction set ...