High-Performance Embedded Computing

142 Chapter 2 CPUs

ALUs, are described as entities. Grouping of operations into functional units are

implemented as VHDL entities.

LISA generates VHDL for only some of the processors, leaving some entities

to be implemented by hand. Some of the processor components must be carefully

coded to ensure that register–transfer and physical synthesis will provide accept-

able power and timing. LISA generates HDL code for the top-level entities (pipe-

line/registers/memory), the instruction decoder, and the pipeline decoder.

PEAS/ASIP

Meister

PEAS-III [Ito00; Sas01] synthesizes a processor based on the following five

types of description from the designer.