High-Performance Embedded Computing

94 Chapter 2 CPUs

Shiue and Chakrabarti [Shi89b] developed a simpler cache model that they

showed gave results similar to the Kamble and Ghose model. Their model used

several definitions: add_bs is the number of transitions on the address bus per

instruction; data_bs is the number of transitions on the data bus per instruction;

word_line_size is the number of memory cells on a word line; bit_line_size is

the number of memory cells in a bit line; Em is the energy consumption of a

main memory access; α, β, γ are technology parameters. The energy consump-

tion is given by

Energy = hit_rate * energy_hit + miss_rate * energy_miss (EQ 2-16)

Energy_hit = E_dec ...