High-Performance Embedded Computing

284 Chapter 5 Multiprocessor Architectures

cache that is divided into 16 banks. Each bank can be independently config-

ured as instruction cache, data cache, or scratch pad memory. This allows the

cache to be changed in size as well as the set associativity of the cache to be

changed.

The PEs are connected by the Daytona bus, a high-speed split transaction

bus. Every bus transaction carries a transaction ID that is used to match up the

various parts of the split transaction. A read is performed in two steps. First, the

address is sent in a four-cycle bus operation:

1. Arbitrate for the address bus.

2. Send the transaction data, including transaction ID, ...