HyperTransport™ System Architecture

Introduction

An HT-based system may include processors or expansion buses that have smaller address ranges than the large 1 TeraByte space used by HT. In such cases address translation may be required. For example, the x86 CPU might have a maximum memory address range of 64GB and a PCI bus implementation may be limited to 4GB of memory address space. If addresses are allocated in HT address space beyond the range of the CPU and Expansion bus, then address translation is required.

To illustrate the possible remapping requirement, Figure 21-1 on page 479 depicts an implementation similar to that described in the previous paragraph. This example does not depict a typical implementation, but rather illustrates an extreme case where address remapping ...