February 2003
Intermediate to advanced
592 pages
11h 47m
English
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X86 Instructions and Special Cycles
Another area of x86 compatibly are CPU special cycles. Most IO devices have no interest in special cycle messages. HT supports the delivery of x86 special cycles via SM broadcast messages. These messages are propagated throughout the HT topology, but are mainly of interest to chipset components, memory/cache controllers, etc. The special cycles supported by HT include:
SHUTDOWN — x86 processors beginning with the 80286 generate a shutdown cycle when it experiences a triple fault conditions, some models of x86 processor may also generate shutdown cycles as a result of other failures such as internal processor errors.
HALT — All X86 processors generate a halt special cycle when a HLT (Halt) instruction is executed. ...
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