Digital Circuits & Design, 1st Education by Pearson

4.74 | Chapter 4

4.11.2 | Static-1 Hazards

Without the delay in the gates, the output Z would be constant at 1. The spike is due to the

gate delay and the fact that not every path from on input to the output is the same length.

Consider logic circuit given in Figure 4.70. Let inputs A, S and B are initially in logic-1,

respectively. The output Z is in logic-1 state. Let the propagation delay for all the gates be

the same as t

p

. S changes from logic-1 state to logic-0 state. Z goes to logic-0 due to delay.

Timing diagram is shown in Figure 4.71 giving static-1 hazard.

A = 1

B = 1

S

(1→0)

P(1→0)

Q(0→1)

Z(1→0→1)

P = AS

Q = SB

N(0→1)

(1)

(1)

N = S

FIGURE 4.70 ...