Digital Circuits & Design, 1st Education by Pearson

Logic Description using VHDL | 13.23

-- 4-bit adder

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY fourbitadd IS

PORT (x, y: IN STD_LOGIC_VECTOR(3 DOWNTO0);

cin : IN STD_LOGIC;

sum : OUT STD_LOGIC_VECTOR (3 DOWNTO0);

cout, V: OUT STD_LOGIC);

END fourbitadd;

ARCHITECTURE fouradder_structure OF fourbitadd IS

SIGNAL c: std_logic_vector (4 DOWNTO 0);

COMPONENT full-adder

PORT(x, y, cin: IN STD_LOGIC;

sum, carry: OUT STD_LOGIC);

END

COMPONENT;

COMPONENT XOR2

PORT(x, y : IN STD_LOGIC;

z : OUT STD_LOGIC);

END COMPONENT;

BEGIN

FA0: full-adder PORT MAP(x(0), y(0), Cin, sum(0), c(1));

FA1: full-adder PORT MAP(x(1), y(1), c(1), sum(1), c(2));

FA2: full-adder PORT MAP(x(2), ...