book

Digital Circuits & Design, 1st Education by Pearson

Name: Digital Circuits & Design, 1st Education by Pearson
ISBN: 9789332559080

by D. P. Kothari, J. S. Dhillon

December 2015

Intermediate to advanced

1081 pages

38h

English

Pearson India

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CHAPTER 1 Introduction
1.1 History of Digital Electronics Systems
1.1.1 Evolution of Electronics
1.1.2 Evolution of Transistors
1.1.3 Evolution of ICs
1.2 Signal and Systems
1.3 Analog Signals and Systems
1.3.1 Direct Signals1.3.2 Alternating Signal
1.3.3 Sinusoidal Signal
1.3.4 Waveform1.3.5 Cycle1.3.6 Time Period
1.3.7 Frequency
1.3.8 Peak Value1.3.9 Peak-to-Peak Value1.3.10 Instantaneous Value1.3.11 Periodic Functions
1.4 Digital System and Signals
1.5 Logic Levels and Pulse Waveforms
1.6 Digital Waveform and Binary Information
1.6.1 Data Transfer
1.7 Advantages of Digital Technology
1.8 Limitations of Digital Technology
1.9 Advances in Digital Technology
1.10 Digital Information Storage
1.11 Digital Computing Systems
1.11.1 Advances in Computing Systems
Summary
Multiple Choice Questions
Questions
CHAPTER 2 NUMBER SYSTEM
2.1 Decimal Number System
2.1.1 Conversion of Base-r Number to Decimal Number
2.1.2 Conversion from Decimal Number to Base-r Number
2.1.3 Base-r Arithmetic
2.1.4 Complement Form
2.1.5 Base-r Subtraction using Complement
2.2 Binary Number System
2.2.1 Binary to Decimal Conversion
2.2.2 Decimal to Binary Conversion
2.3 Binary Arithmetic
2.3.1 Binary Addition
2.3.2 Binary Subtraction
2.4 Signed Numbers
2.4.1 Sign Magnitude Representation
2.4.2 One’s Complement (Radix-minus-one Complement)
2.4.3 Two’s Complement (True Complement)
2.5 Binary Subtraction using Complement
2.5.1 Subtraction with 1’s Complement
2.5.2 Binary Subtraction with 2’s Complement
2.6 Binary Multiplication
2.7 Binary Division
2.8 Octal Number System
2.8.1 Octal to Binary Conversion
2.8.2 Binary to Octal Conversion
2.8.3 Octal Arithmetic
2.9 Hexadecimal Number System
2.9.1 Hexadecimal to Binary Conversion
2.9.2 Binary to Hexadecimal Conversion
2.9.3 Hexadecimal to Octal Conversion
2.9.4 Octal to Hexadecimal Conversion
2.9.5 Hexadecimal Arithmetic
2.10 Binary Codes
2.10.1 Weighted and Non-weighted Code
2.10.2 Sequential Codes
2.11 BCD Code
2.11.1 BCD Addition
2.11.2 BCD Subtraction
2.11.3 BCD Subtraction using 9’s Complement
2.11.4 BCD Subtraction using 10’s Complement
2.12 Excess-3 Code
2.12.1 Xcess-3 (XS-3) Addition
2.12.2 Excess-3 (XS-3) Subtraction
2.12.3 Excess-3 (XS-3) Subtraction using 9’s Complement
2.12.4 Excess-3 (XS-3) Subtraction using 10’s Complement
2.13 Gray Code
2.13.1 Binary to Gray Code Conversion
2.13.2 Gray to Binary Code Conversion
2.14 Alphanumeric Code
2.14.1 American Standard Code for Information Interchange (ASCII) Code
2.14.2 Extended Binary-coded Decimal Interchange Code (EBCDIC)
2.14.3 Unicode Characters
2.15 Error Detection Codes
2.15.1 Parity
2.15.2 Block Parity
2.15.3 Five-bit Codes
2.15.4 The Biquinary Code
2.15.5 The Ring Counter Code
2.15.6 Check Sums
2.15.7 Error-correcting Code
2.16 Multi-Precision Numbers
2.16.1 Floating-point Numbers
2.16.2 Binary Floating-point Numbers
2.16.3 IEEE Standard for Floating-point Representation
2.16.4 Arithmetic Operations with Floating-point Numbers
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 3 DIGITAL LOGIC
3.1 Basic Gates
3.1.1 OR Gate
3.1.2 AND Gate
3.1.3 NOT Gate
3.1.4 NAND Gate
3.1.5 NOR Gate
3.1.6 EXCLUSIVE-OR Gate
3.1.7 EXCLUSIVE-NOR Gate
3.2 Positive Logic and Negative Logic
3.3 Inhibit Circuits
3.4 7400-Series Integrated Circuits
3.5 ANSI/IEEE Standard Logic Symbols
3.6 Pulsed Operation of Logic Gates (1/3)
3.6 Pulsed Operation of Logic Gates (2/3)
3.6 Pulsed Operation of Logic Gates (3/3)
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 4 COMBINATIONAL LOGIC DESIGN
4.1 Combinational Circuits
4.2 Boolean Laws and Theorems
4.2.1 Law of Intersection
4.2.2 Law of Union
4.2.3 Law of Identity
4.2.4 Law of Null4.2.5 Law of Tautology or Idempotence
4.2.6 Law of Complement or Negation
4.2.7 Law of Double Negation or Involution
4.2.8 Law of Commutation4.2.9 Law of Association
4.2.10 Law of Distribution
4.2.11 Law of Absorption
4.2.12 Consensus Theorem
4.2.13 Transposition Theorem
4.2.14 De Morgan’s Theorem-I
4.2.15 De Morgan’s Theorem-II
4.3 Sum-of-product and Product-of-sum Form (1/2)
4.3 Sum-of-product and Product-of-sum Form (2/2)
4.4 Karnaugh Map (K-Map)
4.4.1 K-Map Set-Up
4.4.2 Mapping of 0’s and 1’s in the Karnaugh Map
4.4.3 Adjacency Rule
4.4.4 Grouping of 0’s and 1’s
4.4.5 Determination of Simplified Boolean Function in SOP and POS Form
4.5 Karnaugh Map with ‘Don’t Care’ Conditions (1/2)
4.5 Karnaugh Map with ‘Don’t Care’ Conditions (2/2)
4.6 Five-Variable Karnaugh Map (K-Map)
4.7 Six-Variable Karnaugh Map (K-Map)
4.8 Quine–McCluskey Minimization Procedure
4.8.1 Reduction Techniques
4.8.2 Petrick’s Method
4.9 Map-Entered Variable Method
4.10 Realization of Circuit using NAND/NOR Gates Only
4.10.1 AND/OR Conversion to NAND/NAND Networks
4.10.2 AND/OR Conversion to NOR/NOR Networks
4.11 Hazards
4.11.1 Static Hazards
4.11.2 Static-1 Hazards
4.11.3 Static-0 Hazard
4.11.4 Dynamic Hazard (1/4)
4.11.4 Dynamic Hazard (2/4)
4.11.4 Dynamic Hazard (3/4)
4.11.4 Dynamic Hazard (4/4)
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 5 LOGIC CIRCUIT DESIGN: ARITHMETIC OPERATION
5.1 Combinational Circuits
5.2 Binary Adder
5.2.1 Half-Adder
5.2.2 Full-Adder
5.3 Binary Subtractor
5.3.1 Half-Subtractor
5.3.2 Full-Subtractor
5.4 Binary Parallel Adder
5.5 The Look-Ahead Carry Binary Adders
5.6 Combinational Circuit For Complements
5.6.1 One’s Complement
5.6.2 Two’s Complement using Binary Parallel Adder
5.6.3 Multifunction from Binary Parallel Adder
5.7 Binary Subtractor using Parallel Adder
5.7.1 Subtraction with One’s Complement
5.7.2 Subtraction with Two’s Complement
5.8 Binary Multiplier
5.9 Binary Divider
5.10 BCD Adder
5.11 BCD Subtractor using BCD Adder
5.11.1 Nine’s Complement
5.11.2 Subtractor using Nine’s Complement
5.11.3 Ten’s Complement
5.11.4 Subtractor using Ten’s Complement
5.12 Excess-3 (XS-3) Code Adders
5.13 Excess-3 (XS-3) Code Subtractor
5.14 Comparator (1/2)
5.14 Comparator (2/2)
5.15 Parity Generator
5.15.1 Even-Parity Generator
5.15.2 Odd-Parity Generator
5.15.3 Even-Parity Bit Receiver
5.15.4 Odd-Parity Bit Receiver
5.16 Code Converter (1/3)
5.16 Code Converter (2/3)
5.16 Code Converter (3/3)
5.17 Arithmetic Logic Unit
5.17.1 Arithmetic Unit Design
5.17.2 Logic Unit Design
5.17.3 Status Register
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 6 LOGIC CIRCUIT DESIGN: DATA PROCESSING
6.1 Introduction
6.2 Decoders
6.2.1 One-to-Two Line Decoder
6.2.2 Two-to-Four Line Decoder
6.2.3 Three-to-Eight Line Decoder
6.2.4 BCD-to-Decimal Decoder
6.2.5 Combinational Circuit using Decoder
6.2.6 Cascading of Decoders
6.3 Encoders
6.3.1 Four-to-Two Line Binary Encoder
6.3.2 Four-to-Two Line Priority Encoder
6.3.3 Octal-to-Binary Encoder
6.3.4 Octal-to-Binary Priority Encoder
6.3.5 Decimal-to-BCD Encoder
6.3.6 Decimal-to-BCD Priority Encoder
6.4 Multiplexers
6.4.1 Two-to-One Multiplexer
6.4.2 Four-to-One Multiplexer
6.4.3 Eight-to-One Multiplexer
6.4.4 Sixteen-to-One Multiplexer
6.4.5 Cascading of Multiplexers
6.4.6 Cascading of Multiplexers using Enable
6.4.7 Combinational Circuit using Multiplexer (1/2)
6.4.7 Combinational Circuit using Multiplexer (2/2)
6.5 Demultiplexers
6.5.1 One-to-Two Line Demultiplexer
6.5.2 One-to-Four Line Demultiplexer
6.5.3 One-to-Eight Line Demultiplexer
6.5.4 Cascading of Demultiplexers
6.5.5 Cascading of Demultiplexers using Enable
6.5.6 Combinational Circuit using Demultiplexer
6.6 List of IC’s
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 7 FLIP-FLOPS
7.1 Introduction
7.2 Basic Bistable Element
7.3 SR Latch
7.3.1 SR Latch using NOR Gates
7.3.2 Gated SR Latch using NOR Gates
7.3.3 SR Latch using NAND Gates
7.3.4 Gated SR Latch using NAND Gates
7.3.5 Characteristic Equation of SR-Latch
7.3.6 State Transition Diagram of SR Latch
7.3.7 Excitation Table of SR-Latch
7.3.8 SR-Flip-Flop with Asynchronous Inputs
7.4 Triggering of Latches
7.4.1 Positive (or high) Level Triggering
7.4.2 Negative (or low) Level Triggering
7.4.3 Positive (or leading or rising) Edge Triggering
7.4.4 Negative (or low) Level Triggering7.4.5 Generation of Spikes
7.4.6 Generation of Pulse at Rising Edge of Clock Pulse
7.4.7 Generation of Pulse at Falling Edge of Clock Pulse
7.4.8 Latch Versus Flip-Flop
7.5 D-Flip-Flop
7.5.1 Characteristic Equation of D-Flip-Flop
7.5.2 State Transition Diagram of D-Flip-Flop
7.5.3 Excitation Table of D-Flip-Flop
7.6 Flip-Flop Timing
7.7 JK-Flip-Flop
7.7.1 Characteristic Equation of JK-Flip-Flop
7.7.2 State Transition Diagram of JK-Flip-Flop
7.7.3 Excitation Table of JK-Flip-Flop
7.8 T-Flip-Flop
7.8.1 Characteristic Equation of T-Flip-Flop
7.8.2 State Transition Diagram of T-Flip-Flop
7.8.3 Excitation Table of T-Flip-Flop7.9 Race Around Condition
7.10 Master-Slave Flip-Flop
7.11 Edge-Triggered Flip-Flop
7.12 Conversion of Flip-Flops (1/4)
7.12 Conversion of Flip-Flops (2/4)
7.12 Conversion of Flip-Flops (3/4)
7.12 Conversion of Flip-Flops (4/4)
7.13 List of Flip-Flop ICs
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 8 DESIGN OF SEQUENTIAL CIRCUITS
8.1 Introduction
8.2 Notations
8.3 Moore and Mealy Sequential Circuit (1/3)
8.3 Moore and Mealy Sequential Circuit (2/3)
8.3 Moore and Mealy Sequential Circuit (3/3)
8.4 State Reduction
8.4.1 Equivalence Groups
8.4.2 Implication Chart (1/2)
8.4.2 Implication Chart (2/2)
8.5 State Assignment (1/2)
8.5 State Assignment (2/2)
8.6 Design of Clock Sequential Circuit (1/6)
8.6 Design of Clock Sequential Circuit (2/6)
8.6 Design of Clock Sequential Circuit (3/6)
8.6 Design of Clock Sequential Circuit (4/6)
8.6 Design of Clock Sequential Circuit (5/6)
8.6 Design of Clock Sequential Circuit (6/6)
8.7 Asynchronous Sequential Circuit
8.8 Analysis of Asynchronous Sequential Circuit
8.8.1 Fundamental Mode Asynchronous Sequential Circuit without Latches
8.8.2 Pulse Mode Asynchronous Sequential Circuit with Latches
8.9 Problems in Asynchronous Sequential Circuit
8.9.1 Cycles8.9.2 Races8.9.3 Critical Races
8.9.4 Non-critical Races
8.9.5 Hazards8.9.6 Essential Hazards8.10 Asynchronous Sequential Circuit Design
8.11 Algorithmic State Machines
8.11.1 State Box
8.11.2 Decision Box
8.11.3 Conditional Box
8.12 Realization of ASM Charts
8.12.1 Traditional Synthesis from an ASM Chart
8.12.2 Multiplexer Controller Method
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 9 REGISTERS
9.1 Introduction
9.2 Registers
9.2.1 Four-bit Latch
9.2.2 Register
9.3 Register with Parallel Load
9.4 Shift Register
9.5 Serial-In, Serial-Out Shift Register
9.5.1 Left-shift Serial-in, Serial-out Register with D-flip-flop
9.5.2 Left-shift SISO Register with SR-flip-flop
9.5.3 Left-shift SISO Register with Asynchronous Loading
9.5.4 Right-Shift SISO Register
9.8 Universal Shift Register
9.5.5 Bidirectional SISO Register
9.6 Serial-In, Parallel-Out Shift Register
9.7 Parallel-In, Serial-Out, Shift Register
9.7.1 PISO Left-Shift Register
9.7.2 PISO, Right-Shift Register
9.9 Ring Counter
9.10 Johnson Counter
9.10.1 Controlled Circuit of Switch-Tail Ring Counter (or Twisted-Ring Counter) or Johnson Counter
9.10.2 Decoding Count of Johnson Counter
9.11 Serial Adder
9.12 Sequence Generator
9.13 Sequence Detector
9.14 List of Shift Register ICs
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 10 COUNTERS
10.1 Introduction
10.2 Asyncronous or Ripple Counter
10.2.1 Modulus-4 Asynchronous (Ripple) Up Counter
10.2.2 Modulus-3 Asynchronous (Ripples) Up Counter with Decoded Output
10.2.3 Modulus-4 Asynchronous (Ripples) Down Counter
10.2.4 Modulus-4 Asynchronous (Ripples) Up/Down Counter
10.2.5 Modulus-8 Asynchronous (Ripples) Up Counter
10.2.6 Modulus-8 Asynchronous (Ripples) Down Counter
10.2.7 Modulus-8 Asynchronous (Ripples) Up/Down Counter
10.2.8 Modulus-16 Asynchronous (Ripples) Up/Down Counter
10.3 Asynchronous Counter with Parallel Load
10.4 Modulus-M Asynchronous Counter (1/2)
10.4 Modulus-M Asynchronous Counter (2/2)
10.5 Synchronous Counter
10.5.1 Modulus-4 Synchronous Up Counter
10.5.2 Modulus-4 Synchronous Down Counter
10.5.3 Modulus-4 Synchronous UP/Down Counter
10.5.4 Modulus-8 Synchronous Up Counter
10.5.5 Modulus-8 Synchronous Down Counter
10.5.6 Modulus-8 Synchronous UP/Down Counter
10.6 Synchronous Counter with Parallel Load (1/3)
10.6 Synchronous Counter with Parallel Load (2/3)
10.6 Synchronous Counter with Parallel Load (3/3)
10.7 Cascading of Counters
10.7.1 Modulus-6 Counter
10.7.2 Modulus-10 Counter (1/2)
10.7.2 Modulus-10 Counter (2/2)
10.8 Self-Correcting Counters (1/2)
10.8 Self-Correcting Counters (2/2)
10.9 Sequence Generator
10.10 List of Counter ICs
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 11 MEMORY
11.1 Introduction
11.2 Memory Basics
11.2.1 Memory Address
11.2.2 Memory Operation
11.2.3 Capacity
11.3 Classification of Memory Devices
11.3.1 Design Technology11.3.2 Access of Memory Location
11.3.3 Physical Characteristics
11.3.4 Operational Principle
11.4 Read-Only Memory
11.4.1 Design Procedure of ROM
11.5 Programmable Logic Device (PLD)
11.5.1 Programmable Read-Only Memory
11.5.2 Design Procedure of PROM
11.5.3 Programmable Array Logic
11.5.4 Design Procedure of PAL
11.5.5 Programmable Logic Array
11.5.6 Design Procedure of PLA
11.5.7 Programming Mechanisms
11.5.8 Complex-Programmable Logic Device
11.5.9 Field-Programmable Gate Array
11.6 Random Access Memory
11.6.1 Static Random Access Memory
11.6.2 Dynamic Random Access Memory
11.6.3 Types of DRAM
11.7 First-in First-out Memory
11.8 Last-in First-out Memory
11.9 Associative Memory or Content Address Memory
11.9.1 Match Logic
11.10 Memory Expansion
11.10.1 Word Size Expansion
11.10.2 Word Capacity Expansion
11.10.3 Word Size and Capacity Expansion (1/3)
11.10.3 Word Size and Capacity Expansion (2/3)
11.10.3 Word Size and Capacity Expansion (3/3)
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 12 ANALOG-TO-DIGITAL CONVERSION
12.1 Introduction
12.2 Variable Resistor Networks
12.3 Resistive Divider
12.4 Binary Ladder (1/3)
12.4 Binary Ladder (2/3)
12.4 Binary Ladder (3/3)
12.4.1 Analog Output of Binary Ladder Network
12.5 Digital-to-Analog Converter
12.5.1 Multiple Signals
12.6 Specifications of a DAC
12.6.1 Accuracy12.6.2 Resolution
12.6.3 Linearity
12.6.4 Settling Time12.6.5 Temperature Sensitivity
12.7 Analog-to-Digital Converter
12.7.1 Quantization and Encoding
12.8 Simultaneous/Flash ADC
12.9 Counter Type ADC
12.10 Continuous ADC
12.11 Succesive Approximation ADC
12.12 Dual-Slope ADC
12.13 Specification of ADC
12.14 DAC and ADC ICs
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 13 LOGIC DESCRIPTION USING VHDL
13.1 Introduction
13.2 HDL Format and Syntax
13.2.1 Identifiers
13.2.2 Keywords (Reserved Words)
13.2.3 Numbers
13.2.4 Characters, Strings and Bit Strings
13.2.5 Entity Declaration
13.2.6 Architecture Body
13.3 Boolean Description Using VHDL
13.4 Intermediate Signals
13.5 Representing Data in VHDL
13.5.1 Signal13.5.2 Variable13.5.3 Constant
13.5.4 Bit Arrays/Bit Vectors
13.5.5 User-Defined Types
13.6 Libraries
13.7 VHDL Operators
13.7.1 Logic Operators
13.7.2 Relational Operators
13.7.3 Shift Operators
13.7.4 Addition Operators
13.7.5 Unary Operators
13.7.6 Multiplying Operators13.7.7 Miscellaneous Operators
13.8 Structural Modelling
13.8.1 Declarative Part
13.8.2 Statement Part
13.9 Data Flow Modeling
13.9.1 WHEN-ELSE Statement
13.9.2 WITH-SELECT Signal Assignments
13.10 Behavioural Modelling
13.11 Sequential Statements for Behavioural Modelling
13.11.1 IF Statements
13.11.2 CASE Statement
13.11.3 LOOP Statements
13.11.4 WHILE-LOOP Statement
13.11.5 FOR-LOOP Statement
13.11.6 NEXT and EXIT Statement
13.11.7 WAIT Statement
13.11.8 NULL Statement
13.12 Truth Table using VHDL
13.12.1 Truth Tables Using VHDL: Selected Signal Assignment
13.13 Logical Operations on Bit Arrays
13.14 VHDL Subtractor
13.15 Expanding the Bit Capacity of a Circuit
13.15.1 VHDL Generate Statement
13.16 Magnitude Comparator
13.17 VHDL BCD-to-Binary Code Converters
13.18 VHDL Seven-Segment Decoder/Driver
13.19 VHDL Encoder
13.20 VHDL Mux and DeMux
13.21 Sequential Circuits Using VHDL
13.21.1 The D Latch
13.22 Edge-Triggered Devices
13.22.1 D-Flip Flop
13.23 VHDL Circuit with Multiple Components
13.24 Basic Counters using VHDL
13.24.1 State Transition Description Methods13.24.2 State Descriptions in VHDL
13.24.3 Behavioural Description
13.25 Full-Featured Counters in VHDL
13.26 Wiring VHDL Modules Together
13.26.1 Decoding the VHDL MOD-5 Counter
13.27 Registers
13.27.1 VHDL SISO Register
13.27.2 VHDL PISO Register
13.28 VHDL Ring Counters
Summary
Multiple Choice Questions
Questions
Problems
CHAPTER 14 DIGITAL LOGIC FAMILIES
14.1 Introduction
14.2 Logic Families
14.2.1 Bipolar Logic Family14.2.2 Unipolar Logic Family
14.2.3 Requirement of a Logic Family
14.3 Digital IC Specifications
14.3.1 Threshold Voltage
14.3.2 Propagation Delay14.3.3 Power Dissipation
14.3.4 Speed Power Product
14.3.5 Voltage and Current Parameters
14.3.6 Fan-out
14.3.7 Fan-in
14.3.8 Noise Immunity
14.4 Transistor-Transistor Logic
14.4.1 The Bipolar Junction Transistor
14.4.2 TTL Inverter
14.4.3 TTL NAND Gate
14.4.4 TTL NOR Gate
14.5 TTL Parameters
14.5.1 Current Sinking14.5.2 Current Sourcing
14.5.3 Floating Inputs
14.5.4 TTL Loading and Fan-out
14.5.5 Unit Load
14.6 Open-Collector Gates
14.6.1 Wired AND Operation
14.6.2 Three-state TTL
14.6.3 Buffer/Drivers
14.6.4 Schottky TTL
14.7 TTL Subfamilies
14.7.1 Standard TTL, 74 Series
14.7.2 Low-power TTL, 74L Series
14.7.3 High-speed TTL, 74H Series14.7.4 Schottky TTL, 74S Series14.7.5 Low-power Schottky TTL, 74LS Series
14.7.6 Advanced Schottky TTL, 74AS Series
14.7.7 Advanced Low-power Schottky TTL, 74ALS Series14.7.8 Fast TTL, 74F Series14.8 External Drive for TTL Loads
14.8.1 Switch Drive
14.8.2 Size of Pull-Up Resistance14.8.3 Transistor Drive14.8.4 Operational Amplifier Drive
14.8.5 Comparator Drive
14.9 TTL Driving External Loads
14.9.1 Supply Voltage Different from +5 V
14.10 Integrated Injection Logic
14.10.1 IIL OR I2L Inverter
14.10.2 IIL OR I2L NAND Gate
14.10.3 IIL OR I2L NOR Gate
14.11.1 Basic ECL Circuit
14.11.2 ECL OR/NOR Gate14.11.3 ECL Subfamilies14.11.4 Wired OR Connections14.11 Emitter-Coupled Logic
14.11.5 Interfacing ECL Gates
14.12 MOS Logic
14.12.1 Symbols and Switching Action of MOS
14.12.2 Resistor
14.12.3 NMOS Inverter
14.12.4 NMOS NAND Gate
14.12.5 NMOS NOR Gate
14.13 CMOS Logic
14.13.1 CMOS Inverter
14.13.2 CMOS NAND Gate
14.13.3 CMOS NOR Gate
14.13.4 Buffered and Un-buffered Gates
14.13.5 Transmission Gate
14.13.6 Open Drain and High Impedance Outputs
14.14 Characteristics of CMOS
14.15 Dynamic MOS Logic
14.15.1 Dynamic MOS Inverter
14.15.2 Dynamic MOS NAND Gate
14.15.3 Dynamic MOS NOR Gate
14.16 Interfacing
14.16.1 TTL to CMOS
14.16.2 CMOS to TTL
14.16.3 TTL to ECL
14.16.4 ECL to TTL
Summary
Multiple Choice Questions
Questions
CHAPTER 15 CLOCKS AND TIMING CIRCUITS
15.1 Introduction15.1.1 Astable Multivibrator
15.1.2 Monostable Multivibrator
15.1.3 Bistable Multivibrator
15.2 Logic Gates in Timing Circuits
15.2.1 Astable (Free-running) Multivibrator
15.2.2 Monostable Multivibrator
15.3 Operational Amplifier
15.4 Schmitt Trigger (Regenerative Comparator)
15.4.1 Limiting Output Voltage
15.5 Astable Multivibrator using OP-AMP
15.6 Monostable Multivibrator using OP-AMP
15.7 Timer 555
15.8 Monostable Multivibrator using Timer
15.8.1 Operation of the Monostable Multivibrator
15.9 Astable Multivibrator Using Timer
15.9.1 Duty Cycle
Summary
Multiple Choice Questions
Questions
Problems
Bibliography
Index (1/2)
Index (2/2)

Content preview from Digital Circuits & Design, 1st Education by Pearson

8.66 | Chapter 8

Present state D (Figure 8.52(e))

When input, X is 1, the next state is E having output, Z as 0 because the fourth bit of

sequence is 1 and complete sequence 1001 is detected and next sequence is expected.

If input, X is 0 then next state is A having output, Z as 0 because fourth bit of sequence

is not correctly detected. Out of received sequence 1000, 0 is accepted hence next state

becomes A.

FIGURE 8.52(e) | Partial state diagram

Present state E (Figure 8.52(f))

When input, X is 0, the next state is F having output, Z as 0 because the fth bit of sequence

is 0 and complete sequence 10010 is detected and next ...

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Digital Systems: Principles and Design by Pearson

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ISBN: 9789332559080

Cloud Computing

Data Engineering

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Digital Circuits & Design, 1st Education by Pearson

by D. P. Kothari, J. S. Dhillon

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