Digital Circuits & Design, 1st Education by Pearson

10.8 | Chapter 10

C

P

A

0

A

1

01

1

0

01

0

1

10

01

t

0

t

1

t

2

t

3

t

4

FIGURE 10.10 | Timing diagram of MOD-4 asynchronous down counter

• Input, T

0

is 1 so output A

0

of T-ip-op, FF0 changes from 0 to 1 during the applied

falling edge of clock pulse, C

P

0

. Inverted output, Q

0

of ip-op FF0 changes from

1to 0. It acts as falling edge clock pulse, C

P

1

to T-ip-op, FF1 and input T

1

is 1 so

output, A

1

of T-ip-op, FF1 changes from 1 to 0.

• Input, T

0

is 1, so output, A

0

of T-ip-op, FF0 changes from 1 to 0 during the applied

falling edge of clock pulse, C

P

0

. Since, A

0

changes from 1 to 0. Inverted output, Q

0

of

T-ip-op, FF0 changes from 0 to 1 which acts as clock ...