Digital Circuits & Design, 1st Education by Pearson

Logic Description using VHDL | 13.57

incremented. Otherwise, it should recycle the counter to zero. The last statement connects

the counter value to the output pins of the device.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY counter IS

PORT (clock : IN BIT; q : OUT INTEGER RANGE 0 TO 4);

END counter;

ARCHITECTURE counter_a OF counter IS

BEGIN

PROCESS (clock)

VARIABLE count: INTEGER RANGE 0 TO 4;

BEGIN

IF (clock = ‘1’ AND clock’ EVENT) THEN

If count < 4 THEN

count: = count + 1; --increment value

ELSE

count : = 0; --recycle to zero

END IF;

END IF;

q <= count; --transfer register contents to outputs

END PROCESS;

END counter_a;

FIGURE 13.60 | Behavioural description ...