Digital Circuits & Design, 1st Education by Pearson

5.70 | Chapter 5

Rewriting above equation,

Pxxx xxxx x

odd

=⊕ ⊕+

⊕⊕

()()()

()

3210 3210

Rewriting above equation,

Pxxxx

odd

=⊕⊕⊕()

()

32 10

(5.95)

Combinational circuit is given in Figure 5.73.

x

0

x

1

x

2

x

3

P

od

d

FIGURE 5.73 | Odd-parity generator

5.15.3 | Even-Parity Bit Receiver

On receiving the digital data, a parity checking circuit generates an error signal if the

total number of 1’s is even in an even-parity system. The even-parity checker detects a

single-bit error.

The total number of 1 bit in the word including the even-parity bit should be even.

Combinational circuit is given in Figure 5.74. Table 5.17 gives the error bit for even-parity

checker.

x

0