Digital Circuits & Design, 1st Education by Pearson

Digital Logic Families | 14.67

• The speed of the CMOS gate increases with increase in V

DD

.

• The noise margin of CMOS gates is 30 per cent of V

DD

. Therefore, they are very much

preferred in noisy environments.

• At higher frequencies, the CMOS loses some of its advantages over the other logic

families.

• The fan-out of CMOS gates depends on the maximum permissible value of the prop-

agation delay. The propagation delay of a CMOS gate increases with increase in load.

• Each CMOS load increases the propagation delay of the driving circuit by 3 ns,

because each CMOS input typically presents a 5 pF load to ground.

• The CMOS has large fan-out ...