Solid State Electronic Devices, 7th Edition

Problems

1. 6.1 Assume the JFET shown in Fig. 6–6 is Si and has p⁺ regions doped with 10¹⁸ acceptors/cm³ and a channel with 10¹⁶ donors/cm³. If the channel half-width a is 1 µm, compare V_P with V₀. What voltage V_GD is required to cause pinch-off when V₀ is included? With V_G = –3 V, at what value of V_D does the current saturate?

2. 6.2 If the ratio Z/L = 10 for the JFET of Prob. 6.1 , and µ_n = 1000 cm²/V−s, calculate I_D(sat.) for V_G = 0, –2, –4, and –6V. Plot I_D(sat.) vs. V_D(sat.).

3. 6.3 For the JFET of Prob. 6.2 , plot I_D vs. V_D for the same four values of V_G. Terminate each plot at the point of saturation.

4. 6.4 Use Eqs. (6–9) and (6–10) to calculate and plot I_D(V_D,V_G) at 300 K for a Si JFET with a = 1000 Å, Nd = 7 × 10¹⁷cm^–3, Z = 100 µm, and L = 5 µm. ...