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Solid State Electronic Devices, 7th Edition
book

Solid State Electronic Devices, 7th Edition

by Ben Streetman, Sanjay Banerjee
March 2014
Intermediate to advanced content levelIntermediate to advanced
624 pages
26h 33m
English
Pearson
Content preview from Solid State Electronic Devices, 7th Edition

Problems

  1. 6.1 Assume the JFET shown in Fig. 6–6 is Si and has p+ regions doped with 1018 acceptors/cm3 and a channel with 1016 donors/cm3. If the channel half-width a is 1 µm, compare VP with V0. What voltage VGD is required to cause pinch-off when V0 is included? With VG = –3 V, at what value of VD does the current saturate?

  2. 6.2 If the ratio Z/L = 10 for the JFET of Prob. 6.1 , and µn = 1000 cm2/V−s, calculate ID(sat.) for VG = 0, –2, –4, and –6V. Plot ID(sat.) vs. VD(sat.).

  3. 6.3 For the JFET of Prob. 6.2 , plot ID vs. VD for the same four values of VG. Terminate each plot at the point of saturation.

  4. 6.4 Use Eqs. (6–9) and (6–10) to calculate and plot ID(VD,VG) at 300 K for a Si JFET with a = 1000 Å, Nd = 7 × 1017cm–3, Z = 100 µm, and L = 5 µm. ...

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Publisher Resources

ISBN: 9780137577866