book

Solid State Electronic Devices, 7th Edition

Name: Solid State Electronic Devices, 7th Edition
ISBN: 9780137577866

by Ben Streetman, Sanjay Banerjee

March 2014

Intermediate to advanced

624 pages

26h 33m

English

Pearson

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Solid State Electronic Devices
Solid State Electronic Devices
Contents
Preface
GoalsWhat is New in this EditionReading ListsProblemsUnitsPresentation
Prentice Hall Series In Solid State Physical Electronics
About the Authors
Solid State Electronic Devices
Chapter 1 Crystal Properties and Growth of Semiconductors
Objectives
1.1 Semiconductor Materials
1.2 Crystal Lattices
1.2.1 Periodic Structures1.2.2 Cubic LatticesSolution1.2.3 Planes and Directions1.2.4 The Diamond LatticeSolution

1.3 Bulk Crystal Growth
1.3.1 Starting Materials1.3.2 Growth of Single-Crystal Ingots1.3.3 Wafers1.3.4 DopingSolution
1.4 Epitaxial Growth
1.4.1 Lattice-Matching in Epitaxial Growth1.4.2 Vapor-Phase Epitaxy1.4.3 Molecular Beam Epitaxy
1.5 Wave Propagation in Discrete, Periodic Structures
Summary
Problems
Reading List
Self Quiz
Chapter 2 Atoms and Electrons
Objectives
2.1 Introduction to Physical Models
2.2 Experimental Observations
2.2.1 The Photoelectric Effect2.2.2 Atomic Spectra
2.3 The Bohr Model
Solution
2.4 Quantum Mechanics
2.4.1 Probability and the Uncertainty Principle2.4.2 The Schrödinger Wave Equation2.4.3 Potential Well ProblemSolution2.4.4 Tunneling
2.5 Atomic Structure and the Periodic Table
2.5.1 The Hydrogen Atom2.5.2 The Periodic Table
Summary
Problems
Reading List
Self Quiz
Chapter 3 Energy Bands and Charge Carriers in Semiconductors
Objectives
3.1 Bonding Forces and Energy Bands in Solids
3.1.1 Bonding Forces in Solids3.1.2 Energy Bands3.1.3 Metals, Semiconductors, and Insulators3.1.4 Direct and Indirect Semiconductors3.1.5 Variation of Energy Bands with Alloy Composition
3.2 Charge Carriers in Semiconductors
3.2.1 Electrons and HolesSolution3.2.2 Effective MassSolution3.2.3 Intrinsic Material3.2.4 Extrinsic MaterialSolution3.2.5 Electrons and Holes in Quantum Wells
3.3 Carrier Concentrations
3.3.1 The Fermi Level3.3.2 Electron and Hole Concentrations at EquilibriumSolutionSolution3.3.3 Temperature Dependence of Carrier Concentrations3.3.4 Compensation and Space Charge Neutrality
3.4 Drift of Carriers in Electric and Magnetic Fields
3.4.1 Conductivity and MobilitySolution3.4.2 Drift and Resistance3.4.3 Effects of Temperature and Doping on MobilityExample 3–7 Solution3.4.4 High-Field Effects3.4.5 The Hall EffectSolution
3.5 Invariance of the Fermi Level at Equilibrium
Summary
Problems
Reading List
Self Quiz
Chapter 4 Excess Carriers in Semiconductors
Objectives
4.1 Optical Absorption1
4.2 Luminescence
4.2.1 PhotoluminescenceSolution4.2.2 Electroluminescence
4.3 Carrier Lifetime and Photoconductivity
4.3.1 Direct Recombination of Electrons and Holes4.3.2 Indirect Recombination; Trapping4.3.3 Steady State Carrier Generation; Quasi-Fermi Levels4.3.4 Photoconductive Devices
4.4 Diffusion of Carriers
4.4.1 Diffusion Processes4.4.2 Diffusion and Drift of Carriers; Built-in Fields4.4.3 Diffusion and Recombination; The Continuity Equation4.4.4 Steady State Carrier Injection; Diffusion LengthSolution4.4.5 The Haynes–Shockley ExperimentSolution4.4.6 Gradients in the Quasi-Fermi Levels
Summary
Problems
Reading List
Self Quiz
Chapter 5 Junctions
Objectives
5.1 Fabrication of p-n Junctions
5.1.1 Thermal Oxidation5.1.2 Diffusion5.1.3 Rapid Thermal Processing5.1.4 Ion Implantation5.1.5 Chemical Vapor Deposition (CVD)5.1.6 Photolithography5.1.7 Etching5.1.8 Metallization
5.2 Equilibrium Conditions
5.2.1 The Contact PotentialExample 5–1Solution5.2.2 Equilibrium Fermi Levels5.2.3 Space Charge at a JunctionSolution
5.3 Forward- and Reverse-Biased Junctions; Steady State Conditions
5.3.1 Qualitative Description of Current Flow at a Junction5.3.2 Carrier InjectionSolution5.3.3 Reverse BiasSolution
5.4 Reverse-Bias Breakdown
5.4.1 Zener Breakdown5.4.2 Avalanche Breakdown5.4.3 Rectifiers5.4.4 The Breakdown Diode
5.5 Transient and A-C Conditions
5.5.1 Time Variation of Stored Charge5.5.2 Reverse Recovery TransientSolution5.5.3 Switching Diodes5.5.4 Capacitance of p-n JunctionsSolution5.5.5 The Varactor Diode
5.6 Deviations from the Simple Theory
5.6.1 Effects of Contact Potential on Carrier Injection5.6.2 Recombination and Generation in the Transition Region5.6.3 Ohmic Losses5.6.4 Graded Junctions
5.7 Metal–Semiconductor Junctions
5.7.1 Schottky Barriers5.7.2 Rectifying Contacts5.7.3 Ohmic Contacts5.7.4 Typical Schottky Barriers
5.8 Heterojunctions
Solution
Summary
Problems
Reading List
Self Quiz
Chapter 6 Field-Effect Transistors
Objectives
6.1 Transistor Operation
6.1.1 The Load Line6.1.2 Amplification and Switching
6.2 The Junction Fet
6.2.1 Pinch-off and Saturation6.2.2 Gate Control6.2.3 Current–Voltage Characteristics
6.3 The Metal–Semiconductor Fet
6.3.1 The GaAs MESFET6.3.2 The High Electron Mobility Transistor (HEMT)6.3.3 Short Channel Effects
6.4 The Metal–Insulator–Semiconductor Fet
6.4.1 Basic Operation and Fabrication6.4.2 The Ideal MOS Capacitor6.4.3 Effects of Real SurfacesWork Function DifferenceInterface Charge6.4.4 Threshold VoltageSolution6.4.5 MOS Capacitance–Voltage Analysis6.4.6 Time-Dependent Capacitance Measurements6.4.7 Current–Voltage Characteristics of MOS Gate Oxides
6.5 The Mos Field-Effect Transistor
6.5.1 Output Characteristics6.5.2 Transfer CharacteristicsSolution6.5.3 Mobility Models6.5.4 Short Channel MOSFET I–V Characteristics6.5.5 Control of Threshold VoltageChoice of Gate ElectrodeControl of CiThreshold Adjustment by Ion Implantation6.5.6 Substrate Bias Effects—the “Body” EffectSolution6.5.7 Subthreshold Characteristics6.5.8 Equivalent Circuit for the MOSFET6.5.9 MOSFET Scaling and Hot Electron Effects6.5.10 Drain-Induced Barrier Lowering6.5.11 Short Channel Effect and Narrow Width Effect6.5.12 Gate-Induced Drain Leakage
6.6 Advanced Mosfet Structures
6.6.1 Metal Gate-High-k6.6.2 Enhanced Channel Mobility Materials and Strained Si FETs6.6.3 SOI MOSFETs and FinFETs
Summary
Problems
Reading List
Self Quiz
Chapter 7 Bipolar Junction Transistors
Objectives
7.1 Fundamentals of BJT Operation
7.2 Amplification with BJTS
Example 7–1 Solution
7.3 BJT Fabrication
7.4 Minority Carrier Distributions and Terminal Currents
7.4.1 Solution of the Diffusion Equation in the Base Region7.4.2 Evaluation of the Terminal CurrentsExample 7–2 Solution7.4.3 Approximations of the Terminal Currents7.4.4 Current Transfer RatioSolution
7.5 Generalized Biasing
7.5.1 The Coupled-Diode ModelExample 7–4 Solution7.5.2 Charge Control Analysis
7.6 Switching
7.6.1 Cutoff7.6.2 Saturation7.6.3 The Switching Cycle7.6.4 Specifications for Switching Transistors
7.7 Other Important Effects
7.7.1 Drift in the Base Region7.7.2 Base Narrowing7.7.3 Avalanche Breakdown7.7.4 Injection Level; Thermal Effects7.7.5 Base Resistance and Emitter Crowding7.7.6 Gummel–Poon Model7.7.7 Kirk Effect
7.8 Frequency Limitations of Transistors
7.8.1 Capacitance and Charging Times7.8.2 Transit Time Effects7.8.3 Webster Effect7.8.4 High-Frequency Transistors
7.9 Heterojunction Bipolar Transistors
Summary
Problems
Reading List
Self Quiz
Chapter 8 Optoelectronic Devices
Objectives
8.1 Photodiodes
8.1.1 Current and Voltage in an Illuminated JunctionSolution8.1.2 Solar CellsSolution8.1.3 Photodetectors8.1.4 Gain, Bandwidth, and Signal-to-Noise Ratio of Photodetectors
8.2 Light-Emitting Diodes
8.2.1 Light-Emitting Materials8.2.2 Fiber-Optic CommunicationsSolution
8.3 Lasers
8.4 Semiconductor Lasers
8.4.1 Population Inversion at a Junction8.4.2 Emission Spectra for p-n Junction Lasers8.4.3 The Basic Semiconductor Laser8.4.4 Heterojunction LasersSeparate Confinement and Graded Index Channels.Vertical Cavity Surface-Emitting Lasers (VCSELs).8.4.5 Materials for Semiconductor Lasers8.4.6 Quantum Cascade Lasers
Summary
Problems
Reading List
Self Quiz
Chapter 9 Integrated Circuits
Objectives
9.1 Background
9.1.1 Advantages of Integration9.1.2 Types of Integrated Circuits
9.2 Evolution of Integrated Circuits
9.3 Monolithic Device Elements
9.3.1 CMOS Process Integration9.3.2 Integration of Other Circuit ElementsDiodes.Resistors.Capacitors.Inductors.Contacts and Interconnections.
9.4 Charge Transfer Devices
9.4.1 Dynamic Effects in MOS Capacitors9.4.2 The Basic CCD9.4.3 Improvements on the Basic Structure9.4.4 Applications of CCDs
9.5 Ultra Large- Scale Integration (ULSI)
9.5.1 Logic Devices9.5.2 Semiconductor MemoriesSRAMs.DRAMs.Flash Memories.
9.6 Testing, Bonding, and Packaging
9.6.1 Testing9.6.2 Wire Bonding9.6.3 Flip-Chip Techniques9.6.4 Packaging
Summary
Problems
Reading List
Self Quiz
Chapter 10 High-Frequency, High-Power and Nanoelectronic Devices
Objectives
10.1 Tunnel Diodes
10.1.1 Degenerate Semiconductors
10.2 The Impatt Diode
10.3 The Gunn Diode
10.3.1 The Transferred-Electron Mechanism10.3.2 Formation and Drift of Space Charge Domains
10.4 The P-N-P-N Diode
10.4.1 Basic Structure10.4.2 The Two-Transistor Analogy10.4.3 Variation of α with Injection10.4.4 Forward-Blocking State10.4.5 Conducting State10.4.6 Triggering Mechanisms
10.5 The Semiconductor- Controlled Rectifier
10.5.1 Turning Off the SCR
10.6 Insulated-Gate Bipolar Transistor
10.7 Nanoelectronic Devices
10.7.1 Zero-Dimensional Quantum Dots10.7.2 One-Dimensional Quantum Wires10.7.3 Two-Dimensional Layered Crystals10.7.4 Spintronic Memory10.7.5 Nanoelectronic Resistive Memory
Summary
Problems
Reading List
Self Quiz
Appendix I Definitions of Commonly Used Symbols1
Appendix II Physical Constants and Conversion Factors1
Appendix III Properties of Semiconductor Materials
Appendix IV Derivation of the Density of States in the Conduction Band
Appendix V Derivation of Fermi–Dirac Statistics
Appendix VI Dry and Wet Thermal Oxide Thickness Grown on Si (100) as a Function of Time and Temperature1
Appendix VII Solid Solubilities of Impurities in Si1
Appendix VIII Diffusivities of Dopants in Si and SiO21
Appendix IX Projected Range and Straggle as Function of Implant Energy in Si1
Answers to Selected Self Quiz Questions
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Index
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Z
Semiconductor Physics
p-n Junctions
MOS-n Channel
BJT-p-n-p

Content preview from Solid State Electronic Devices, 7th Edition

Problems

9.1 Assume that boron is diffused into a uniform n-type Si sample, resulting in a net doping profile N_a(x) – N_d Set up an expression relating the sheet resistance of the diffused layer to the acceptor profile N_a(x) and the junction depth x_j Assume that N_a(x) is much greater than the background doping N_d over most of the diffused layer.
9.2 A typical sheet resistance of a base diffusion layer is 200Ω/square.
1. What should be the aspect ratio of a 10-kΩ resistor, using this diffusion?
2. Draw a pattern for this resistor (see Fig. 9–12b) which uses little area for a width w = 5 μm.
9.3 A 3-μm n-type epitaxial layer (N_d = 10¹⁶ cm^–3) is grown on a p-type Si substrate. Areas of the n layer are to be junction isolated (see Fig. 9–12a ...

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Solid State Electronic Devices, 7th Edition

by Ben Streetman, Sanjay Banerjee

Problems

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