At a given moment, a port may have a number of packets ready to transmit:
Data packets may be queued up in one or more of the data VL transmit buffers (VL[14:0]).
The port's SMI may need to transmit an SMP:
- The SM may live behind this port's SMI and it needs to send an SMP request to another device in the fabric.
- This port may need to send an SMP response or a SubnTrap(Notice) back to the SM.
One or more of the data VL receive buffers may need to send link-level Flow Control Packets (FCPs) to their respective data VL transmit buffers on the other end of the link.
In a port that only implements a single data VL (VL0), the question remains: In what order do these entities (the data VL, the SMP ...