Operating Systems: Concurrent and Distributed Software Design

4.7. Scheduling for shared-memory multiprocessors

Section 1.3.3 introduced shared-memory multiprocessors and Chapter 3 discussed the allocation of devices to processors and interrupt handling. Chapter 5 describes the memory hierarchy in a computer system, including a hardware-controlled cache and an address translation unit. In a shared-memory multiprocessor each processor has a separate cache and address translation unit.

A given processor may have a local run queue for the device handlers of any dedicated devices it might have. There are also likely to be one or more global run queues. A possible approach is that a processor, on becoming free, should execute code such that it first examines its local run queue and, if that contains no run-nable ...