Operating Systems: Concurrent and Distributed Software Design

5.8. An example of a memory management unit (MMU)

Figure 5.14 shows the basic design of the MIPS R2000 (also R3000) chip. As well as a RISC processor there is also a system control coprocessor on the chip. This includes a memory management unit which is shown in more detail in the figure. The MMU contains a simple TLB with space for 64 entries. Each non-empty entry in the TLB indicates a page in the virtual memory of a process and its corresponding location in physical memory (see Figure 5.15). The TLB is managed by the operating system; before a page can be addressed it must be in main memory and have an entry in the TLB. The MMU contains four registers: entry-hi, entry-lo, index and random. The operating system uses them to insert or replace ...