The first integrator is shown in Figure 8.16, and it operates as follows. During ck
1
,
the input voltage V
in
is sampled onto C
sampling
. During ck
2
, a charge proportional to
the voltage difference between V
in
and DAC reference voltage V
ref
is transferred from
C
sampling
to C
integrating
.
The sampling and integrating capacitances were specified earlier in Table 8.4 and
are denoted here in Figure 8.16. The input common-mode voltage, V
cm_i
is set
to 0.9 V for a 2.5-V power supply, thereby allowing switches S
3
and S
4
to be
implemented using only NMOS devices. The sizing of the switches is listed ...
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