this circuit makes use of two comparators in addition to two logic gates (XOR and
NOR) to realize the subconverters. In this confi guration, when Φ
2
=1, C
s
may be
connected to one of three potentials: +V
ref
, −V
ref
, and ground, depending on the
comparator’s output. Similar to the preceding analysis of the 1-bit pipelined stage, we
can find the ideal input/output relationship of the 1.5-bit pipelined stage as follows:
V
VVifVV
VifV
out
inrefinref
inr
=
−>
−
2025
2025
,.
,.
eefinref
inrefinref
VV
VVifVV
<<
+<−
025
2025
.
,.
(5.54)
Here, we also assume that the capacitance of C
s
is equal to that of C
f
. As ...
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