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Demystifying Switched Capacitor Circuits
book

Demystifying Switched Capacitor Circuits

by Mingliang (Michael) Liu
June 2006
Intermediate to advanced content levelIntermediate to advanced
336 pages
10h 24m
English
Newnes
Content preview from Demystifying Switched Capacitor Circuits
Switched-Capacitor Building Blocks
69
should design the S&H circuit in such a way that the effective holding capacitance
appearing in the holding mode is maximized; while that appearing in the sampling
mode is minimized.
A simple CMOS S&H circuit built based on this concept is shown in Figure 3.7(c)
[49]. Note that this circuit looks identical to that of Figure 3.7(a) except for the capaci-
tor C
0
between node A and the output. During the sampling mode (Φ
1
1), the input
V
in
is sampled by an effective holding capacitance C
h_s
= (C
h
+ C
0
). During the holding
mode, the effective Miller holding capacitance that appears at node A is given by
CG
CC
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Publisher Resources

ISBN: 9780750679077