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Demystifying Switched Capacitor Circuits
book

Demystifying Switched Capacitor Circuits

by Mingliang (Michael) Liu
June 2006
Intermediate to advanced content levelIntermediate to advanced
336 pages
10h 24m
English
Newnes
Content preview from Demystifying Switched Capacitor Circuits
Design of SC Delta-Sigma Modulators for Multistandard RF Receivers
295
Additionally, the use of delayed clock phases ck
1d
and ck
2d
reduces the charge
injection errors [35]. S
5
resets the integrating capacitors during the power-on mode or
the switching mode (when the modulator is being transformed to support a new
standard). In addition, S
5
serves as a clipper, resetting the modulator’s output when it
is overloaded or unstable [22].
The second integrator is shown in Figure 8.17. The input common-mode voltage,
V
cm_i
is set to 0.9 V, and the midsupply reference voltage, V
mid
is set to 1.25 V for a
2.5-V supply. The feedback branch that creates the ...
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Publisher Resources

ISBN: 9780750679077