
Demystifying Switched-Capacitor Circuits
168
capacitor-interpolating or folding fl ash ADCs, multistage SC preamplifi ers or com-
parators [11] have been used to reduce the clock feedthrough as well as input-referred
offset errors. The use of multistage SC comparators, although providing a better
accuracy performance, may limit the overall speed of the fl ash ADC. Specifi cally, a
cascade of M comparators has a time constant approximately given by (assuming all
comparators are identical [11])
τ
µ
≅
4
3
2
0
ML A
V
neff
(5.46)
where L is the length of the input transistor(s), A
0
is the dc gain of each comparator,
and V
eff
is the effective gate-source voltag