We realize from the preceding that the SC confi guration around C
1
and C
2
is equiva-
lent to a sample-and-hold (S&H) with a one-half voltage gain.
After Φ
2
is turned off, the next least significant bit B
M−1
enters. Applying the
principle of charge conservation to the system, we can find the output voltage at the
end of the second bit-conversion cycle, which is given by
V
BVCBVCBVC
C
out
refMrefMref
M
2
22
1
112
(
)
=
++
(
)
−
//
112
1
22+
(
)
=+
−
C
B
B
V
M
M
ref
(5.30)
This process continues till the end of the Mth bit-conversion cycle, and it can be
found that the desired analog output v ...
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