Interconnecting two or more ideal voltage sources in a loop may lead to a degenerate circuit
at times. Similarly, interconnecting two or more ideal current sources in series may lead to
a degenerate circuit.
Consider the interconnection of two ideal independent voltage sources as shown in
Fig. 2.3-1. KVL requires that v
s1
(t) v
s2
(t) 0. Therefore, v
s1
(t) has to be equal to v
s2
(t)
at all time instants. If they are not equal to each other, then, either KVL has to yield or the
ideal sources have to yield. KVL cannot yield since it is only a disguised form of law of con-
servation of energy. Therefore, KVL has to ...
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