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The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition
book

The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition

by Lyla B. Das
May 2024
Intermediate to advanced content levelIntermediate to advanced
665 pages
23h 2m
English
Pearson India
Content preview from The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition
PERIPHERAL INTERFACING – II 387
mask status, OCW1 can be read. For example, to mask the interrupt requests on IR0, IR3 and IR7, OCW1
has to have the value.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
10001001
i.e., 89H
Example 10.20
Write instructions to read the current status of the IMR. After that, change the masking structure such that
only IR0 is masked.
Solution
e status of the IMR is to be read, read the status of OCW1.  e instruction is,
IN AL, 0C2H ;C2H is the address we have used in
Example 10.19 and it is the same as that of
ICW2 (with A0 = 1)
MOV AL, 01 ;mask bit for IR0 is set
MOV BL, AL
OUT 0C2H, AL ;send to OCW1
10.3.8.2 | OCW2 (Operational ...
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Publisher Resources

ISBN: 9781282663169