The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition

426 THE x86 MICROPROCESSORS

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

0–Memory'-'to'-'memory disable

1–Memory'-'to'-'memory enable

0–Channel 0 address hold disable

1–Channel 0 address hold enable

X–If bit D

0

'='0

0–Controller enable

1–Controller disable

0–Normal timing

1–Compressed timing

X–If bit D

0

'='1

0–Fixed priority

1–Rotating priority

0–Late write selection

1–Extended write selection

X–If bit 3'='1

0–DREQ sense active high

1–DACK sense active high

1–DREQ sense active low

0–DACK sense active low

Figure 11.24 | Status of the command register

set every time a terminal count is reached by that channel or an external EOP is applied.  ese

bits are cleared upon reset and on each status ...