May 2024
Intermediate to advanced
665 pages
23h 2m
English
book
The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition
by Lyla B. Das
Content preview from The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition
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appendix e
80
x
87 instruction set (
x
87 – pentium)
Legend
Generals
reg = fl oating point register, st(0), st(1) ... st(7)
mem = memory address
mem32 = memory address of 32-bit item
mem64 = memory address of 64-bit item
mem80 = memory address of 80-bit item
FPU Instruction Timings
FX = pairs with FXCH
NP = no pairing
Timings with a hyphen indicate a range of possible timings
Timings with a slash (unless otherwise noted) are latency and
throughput.
Latency is the time between instructions dependent on the
result.
Throughput is the pipeline throughput between non confl icting
instructions.
EA = cycles to calculate the effective address
FPU Instruction Sizing
All FPU instructions that do not access memory are two bytes in length (except FWAIT which
is one byte). ...
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