The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition

SEMICONDUCTOR MEMORY DEVICES 443

clock signal with the CPU and chipset, the chipset has to manipulate the DRAM’s control pins

based on all sorts of timing considerations. SDRAM, however, shares the bus clock with the

CPU. Commands can be placed (or, certain predefi ned combinations of signals) on its control

pins on the rising clock edge.

A signifi cant diff erence between conventional DRAM and SDRAM is the way in which

memory access is executed. In a standard DRAM, the toggling of the external control inputs has

a direct eff ect on the internal memory array. In an SDRAM, the input signals are latched into a

control logic block which functions as the input to a state machine.  erefore, the state machine

actually controls the memory access. Basic ...