May 2024
Intermediate to advanced
665 pages
23h 2m
English
book
The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition
by Lyla B. Das
Content preview from The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition
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MEMORY AND I/O DECODING 235
7.3 | Memory Banks
8086 has a 16-bit memory bus – which means that data transfer can occur at a maximum
rate of 16 bits (one word) per bus cycle. However, sometimes only a byte needs to be accessed.
is means that the processor must have both options – i.e., both byte and word transfer must
be possible. We know that for a word transfer, two byte locations must be accessed i.e., two
addresses are actually needed.
Figure 7.9 | Partial address decoding
A
14
o
A
0
–A
13
16K × 8
RAM
16K × 8
ROM
CS CS
Figure 7.10 | Partial address decoding using two address lines
A
14
A
13
A
0
–A
12
o
8K×8
RAM
8K×8
EPROM
CS
o
CS
236 THE x86 MICROPROCESSORS
Keeping ...
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