Figure 7.6a | Functional block diagram of the 3 to 8 decoder 74LS138
Figure 7.7 | Address decoding of a RAM using a block decoder
CS
A
0
–A
9
A
15
A
16
o
o
A
13
A
10
A
11
A
12
A
14
A
17
A
18
A
19
o
A
Y
3
RAM
1K×8
7
4
L
S
1
3
8
G
1
G
2
A
G
2
B
CB
1
0
1
Inputs
(b)
EnableSelectOutputs
H
H
L
H
H
H
H
H
H
H
X
L
H
H
H
H
H
H
H
H
X
X
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
CBA
X
L
H
L
H
L
H
L
H
H
G1G2*
X
L
L
L
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
H
H
H
H
H
H
H
H
L
Figure 7.6b | Decoding table of 74LS138
NoteG2* = G
2
A and G
2
B
MEMORY AND I/O DECODING 233
e address range is
11111111100000000000
to
11111111101111111111
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