Design Recipes for FPGAs: Using Verilog and VHDL

Design Recipes for FPGAs

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type electrical, more on this later), then the entity would have the

basic form as shown below:

LIBRARY IEEE;

USE IEEE.ELECTRICAL_SYSTEMS.ALL;

ENTITY model IS

GENERIC();

PORT(

TERMINAL p : electrical;

TERMINAL m : electrical

);

END ENTITY;

Notice that as the VHDL-AMS extensions are defined as an

IEEE standard, then the use of a standard library such as electrical

pins requires the use of the electrical_systems.all; packages from

the IEEE library.

Notice that the pins do not have a direction assigned as analog

pins are part of a conserved energy system and are therefore solved

simultaneously.

Mixed-domain modeling

In order to use standard ...