book

Design Recipes for FPGAs: Using Verilog and VHDL

Name: Design Recipes for FPGAs: Using Verilog and VHDL
Author: Peter Wilson
ISBN: 9780080548425

by Peter Wilson

February 2011

Intermediate to advanced

320 pages

10h 19m

English

Newnes

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Chapter 2 An FPGA Primer
IntroductionFPGA evolution
Programmable logic devices
Field programmable gate arrays
FPGA design techniques
Design constraints using FPGAsSummary
Chapter 3 A VHDL Primer The Essentials
Introduction
Entity: model interface
Architecture: model behavior
Process: basic functional unit in VHDL
Basic variable types and operators
Decisions and loops
Hierarchical design
Debugging models
Basic data types
Summary
Chapter 4 Design Automation and Testing for FPGAs
Simulation
Libraries
Synthesis
Physical design flow
Place and route
Timing analysisDesign pitfalls
VHDL issues for FPGA design
Summary
Part 2 Applications
Chapter 5 Images and High-Speed Processing
Introduction
The camera link interface
Getting started
Specifying the interfaces
Defining the top level design
System block definitions and interfaces
The cameralink interface
The PC interface
Summary
Chapter 6 Embedded Processors
IntroductionA simple embedded processor
Soft core processors on an FPGA
Summary
Part 3 Designer's Toolbox
Chapter 7 Serial Communications
IntroductionManchester encoding and decoding
NRZ coding and decoding
NRZI coding and decoding
RS-232
Universal Serial Bus
Summary
Chapter 8 Digital Filters
Introduction
Converting S-domain to Z-domain
Implementing Z-domain functions in VHDL
Basic low pass filter model
FIR filters
IIR filters
Summary
Chapter 9 Secure Systems
Introduction to block ciphersFeistel lattice structures
The Data Encryption Standard (1/2)
The Data Encryption Standard (2/2)
Advanced Encryption Standard
Implementing AES in VHDL (1/3)
Implementing AES in VHDL (2/3)
Implementing AES in VHDL (3/3)
Summary
Chapter 10 Memory
Introduction
Modeling memory in VHDL
Read Only Memory
Random Access Memory
Synchronous RAM
FLASH memory
Summary
Chapter 11 PS/2 Mouse Interface
IntroductionPS/2 mouse basics
PS/2 mouse commands
PS/2 mouse data packetsPS/2 operation modes
PS/2 mouse with wheel
Basic PS/2 mouse handler VHDL
Modified PS/2 mouse handler VHDL
Summary
Chapter 12 PS/2 Keyboard Interface
IntroductionPS/2 keyboard basics
PS/2 keyboard commands
PS/2 keyboard data packetsPS/2 keyboard operation modes
Summary
Chapter 13 A Simple VGA Interface
Introduction
Basic pixel timing
Image handlingVGA interface VHDL
Horizontal sync
Vertical sync
Horizontal and vertical blanking pulses
Calculating the correct pixel data
Summary
Part 4 Optimizing Designs
Chapter 14 Synthesis
Introduction
VHDL supported in RTL synthesis
Some interesting cases where synthesis may fail
What is being synthesized?
Summary
Chapter 15 Behavioral Modeling in VHDL
IntroductionHow to go from RTL to behavioral VHDL
Summary
Chapter 16 Design Optimization
IntroductionTechniques for logic optimization
Improving performance
Critical path analysis
Summary
Chapter 17 VHDL-AMS
Introduction
Introduction to VHDL-AMS
Analog pins: TERMINALS
Mixed-domain modeling
Analog variables: quantities
Simultaneous equations in VHDL-AMS
A VHDL-AMS example
Differential equations in VHDL-AMS
Mixed-signal modeling with VHDL-AMS
A basic switch model
Basic VHDL-AMS comparator model
Multiple domain modeling
Summary
Chapter 18 Design Optimization Example: DES
IntroductionThe DES
Moods
Initial design
Initial synthesis
Optimizing the data path
Final optimization
Results
Triple DES
Comparing the approaches
Summary
Part 5 Fundamental Techniques
Chapter 19 Counters
IntroductionBasic binary counter
Synthesized simple binary counter
Shift register
The Johnson counter
BCD counter
Summary
Chapter 20 Latches, Flip-Flops and Registers
IntroductionLatches
Flip-flops
Registers
Summary
Chapter 21 Serial to Parallel & Parallel to Serial Conversion
Serial to Parallel Conversion
Parallel to Serial Conversion
Summary
Chapter 22 ALU Functions
IntroductionLogic functions
1-bit adder
Structural n-bit addition
Configurable n-bit addition
Twos complement
Summary
Chapter 23 Decoders and Multiplexers
Decoders
Multiplexers
Summary
Chapter 24 Finite State Machines in VHDL
IntroductionState transition diagrams
Implementing FSM in VHDL
Summary
Chapter 25 Fixed Point Arithmetic in VHDL
Introduction
Basic fixed point types
Fixed point functions
Testing the fixed point function
Summary
Chapter 26 Binary Multiplication
IntroductionBasic binary multiplication
VHDL unsigned multiplier
Synthesis of the multiplication function
'Simple' multiplication
Summary
Chapter 27 Bibliography
IntroductionUseful texts for VHDL
Useful Texts for FPGAs
General Digital Design Books
Index
ABCDEFL
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PRSV
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Content preview from Design Recipes for FPGAs: Using Verilog and VHDL

Design Recipes for FPGAs

164

This process returns the current value of the pixel data into a sig-

nal called pixel_data which is declared at the architecture level:

signal pixel_data : std_logic_vector ( 7 downto 0 );

This has the red, green and blue data defined in lowest 6 bits of

the 8 bit data word with the indexes, respectively, of 0–1, 2–3, 4–5.

Horizontal sync

The next key process is the timing of the horizontal and vertical

sync pulses, and the blanking intervals. The line timing for VGA is

31 770 ns per line with a window for displaying the data of 25 170 ns.

If the FPGA is running at 100 MHz (period of 10 ns) then this

means that each line requires ...

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RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

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Design Recipes for FPGAs: Using Verilog and VHDL

by Peter Wilson

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