Design Recipes for FPGAs: Using Verilog and VHDL

then gate the receive data if statement using the DTR signal:

Entity serial_handler is

Port(

Clk : in std_logic;

Nrst : in std_logic;

Data_in : in std_logic;

Data_out : out std_logic;

DTR : in std_logic;

TXD : out std_logic;

RXD : in std_logic

);

End entity serial_handler;

Architecture serial_dtr of serial_handler is

Begin

p1 : process (clk)

Begin

If rising_edge(clk) then

If DTR = '0' then

Data_out <= rxd;

End if;

Txd <= data_in;

End if;

End process p1;

End architecture basic;

Using this type of approach we can extend the serial handler to

incorporate as much or as little of the modem communications link

protocol as we require.

Summary

In this chapter we have introduced ...