Design Recipes for FPGAs: Using Verilog and VHDL

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Design Recipes for FPGAs

if this is included, then the simple VHDL changes slightly to

this form:

Pixel_handler : process (pclk) is

Blank : std_logic_vector (1 downto 0);

Begin

Blank(0) <= hblank or vblank;

Blank(1) <= hblank or vblank;

Red <= data(1 downto 0) & blank;

Green <= data(3 downto 2) & blank;

Blue <= data(5 downto 4) & blank;

End process;

This is the final step and completes the basic VHDL VGA handler.

Summary

This chapter has introduced the basics of developing a simple VGA

handler in VHDL. While it is a simplistic view of the process,

hopefully it has shown how a simple VGA interface can be devel-

oped using not very complex VHDL and a building ...